Core wrapping is a design-for-test solution that handles testing of large system-on-a-chip (i.e., SoC) designs by implementing and executing tests in a same hierarchical manner as the rest of the design steps (i.e., timing and physical design). The core wrapping enables the tests to be inserted and verified by concurrent teams.
Currently available techniques for hierarchical testing using wrapped cores do not address certain situations. Some situations include designs in which multiple wrapped cores are embedded within another wrapped core. Other situations include designs having multiple levels of nested wrapped cores. Conventional testing of hierarchical implementations treat the designs as a single level hierarchical implementation where different hierarchical cores are sitting adjacent to each other.
Referring to FIG. 1, a diagram of a conventional die 20 having a wrapped embedded core 22 is shown. The die 20 has a wrapper 24, an internal scan chain 26, interface logic 28a-28n and an internal test (i.e., INTEST) test compression logic (i.e., TCL) block 30. The wrapped embedded core 22 includes a wrapper 34.
During an internal test mode, the wrapper 24 and the internal scan chain 26 are driven by the internal test TCL block 30. During an external test mode, the wrapper 24 is driven by an external test (i.e., EXTEST) test compression logic block 36 outside the die 20. Instantiating the wrapped core 22 into the die 20 results in a loss of coverage loss of the interface logic 28a-28n. In the internal test mode, the wrapper 34 is in a non-observation mode, so fault effects through the interface logic 28a-28n cannot be observed. In the external test mode, the internal scan chain 26 is not scanned so the interface logic 28a-28n cannot be controlled.
It would be desirable to implement core wrapping in the presence of an embedded wrapped core.